1. Field of the Invention
The present invention generally relates to the manufacture of integrated circuits (ICs) with vertical metal oxide semiconductor field effect transistors (MOSFETs) and, more particularly, to methods for forming a silicon dioxide layer over an array of vertical MOSFETs. The oxide layer serves to separate and electrically insulate the vertical devices from the overpassing interconnect wiring while allowing for self-aligned contacts to be made between the interconnects and the gates of the vertical MOSFETs.
2. Background Description
We propose a method (which we call the xe2x80x9cTop Oxide Methodxe2x80x9d) for forming the oxide layer over an array of vertical transistors, as in a trench DRAM array, in which the access transistors are vertically stacked above the trench capacitors. An insulating layer is needed on top of the active silicon to reduce capacitive coupling between the passing interconnects and the underlying semiconductor components. It is also needed to provide a robust etch stop layer for the reactive ion etch (RIE) patterning of the subsequent interconnect level. Oxide is preferred over silicon nitride since it has a lower dielectric constant and since it allows for standard processing of the self-aligned source junction contacts. This insulating layer must also allow for electrical contact to be made between the passing interconnects and the vertical transistor gates. In addition, the thickness of the layer should be freely adjustable for flexibility in engineering its electrical and structural properties. The process sequence for forming the oxide layer should also permit the implementation of other features such as vertical gate pull-back and vertical gate nitride spacers. The process should also be extendible to shrinking feature sizes.
It is an object of the present invention to provide a method (Top Oxide Method) for forming an insulating layer (Top Oxide) over a vertical device array that satisfies the criteria mentioned above.
According to the method of this invention, the vertical MOSFETs and any underlying structures, such as deep trench capacitors, are formed with a pad nitride in place. Then, after the gate oxide and vertical gate polycrystalline silicon (polysilicon) conductor are formed, any materials deposited on the top of the pad nitride are removed with the polysilicon gate conductor protecting the structures inside the vertical device recess. The gate polysilicon could then be further planarized (e.g., using a chemical-mechanical polish (CMP)) down to the pad nitride, if desired. Once the top surface of the pad nitride is cleared and the gate polysilicon is planarized as desired, the pad nitride is etched away selective to the polysilicon gate conductor and pad oxide which covers the silicon surface. Then, the Top Oxide is deposited. This oxide covers the polysilicon gate plugs that extend above the silicon surface and fills the spaces in between. This oxide is then CMP planarized or otherwise etched back to the tops of the polysilicon plugs.
The resulting structure is a square edged oxide surrounding the gate polysilicon plugs. This square edge makes the process extendible to shrinking ground rules. The Top Oxide thickness is freely adjustable since it is determined solely by the pad nitride thickness that can be increased or decreased as needed. In addition, this method lends itself to additional process options such as a vertical gate pull-back, vertical gate nitride sidewall spacers, and a TTO nitride liner.
In an alternate sequence, the isolation trenches (ITs) can be formed before the Top Oxide is deposited. In this sequence, the pad nitride is kept in place after the vertical devices have been formed and it is used for IT processing. This pad nitride is stripped after the ITs have been etched, filled, and planarized down to this pad nitride. After the pad nitride is stripped, the Top Oxide would be deposited and planarized down to the tops of the gate polysilicon plugs in a manner similar to that of the original sequence.